View ST6G3244MEBJR_8263633.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

november 2011 doc id 022157 rev 2 1/27 1 st6g3244me level translator for sd, sdio, mini sd, and micro sd cards with internal i/o supply and 15 kv esd protection features supports 60 mhz clock rate supports ddr mode for sd card? compliant with ? sd specification part 1 physical layer specification 3.00 (sdr12, sdr25, ddr50) ? sd specification part 1 physical layer specification 2.00 bi-directional with direction control pin balanced propagation delays: t plh t phl ldo power-down support. when the ldo is powered down, v ccb is pulled to gnd via the 130 resistor. when v ccb = 0 v, there is no additional leakage seen on v cca . emi filtering and signal conditioning supports both 1.8 v and 2.9 v data translation on card side integrated ldo to supply 1.8 v or 2.9 v power for b-side i/os (pin-selectable); can be used also externally integrated pull-up and pull-down resistors on b-side operating voltage range ?v cca = 1.62 v to 1.98 v ?v bat = 3.0 v to 5.0 v latch-up performance exceeds 100 ma (jedec standard 78) esd protection for card side (b-port, cd and wp pins) ? 8 kv contact discharge (iec61000-4-2) ? 15 kv air-gap discharge (iec61000-4-2) esd protection for host side (a-side) ? 2 kv hbm (jedec 22-a114) ? 200 v mm (jedec 22-a115) operating temperature range ?40 c to +85 c space-saving flip chip 25 package (2 x 2 x 0.605 mm, 0.4 mm bump pitch) rohs compliant, lead-free soldering capable applications mobile phones, smartphones pdas cameras sd card readers any device with sd memory card table 1. device summary order code package packing package topmark ST6G3244MEBJR flip chip 25 2 x 2 x 0.605 mm, 0.4 mm bump pitch tape and reel (5000 parts per reel) vkh, vkv flip chip 25 www.st.com
contents st6g3244me 2/27 doc id 022157 rev 2 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 passive integration and low-pass emi filter . . . . . . . . . . . . . . . . . . . . . 12 6 data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1 test circuit from host to sd card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 test circuit from sd card to host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.3 measurement of t skew (sd card to host) from rising edge clk.h . . . . . 17 6.4 measurement of t skew.f (read mode) from rising edge clk.h . . . . . . . . . 18 7 low drop-out voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8 sd card specification compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10 tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
st6g3244me list of tables doc id 022157 rev 2 3/27 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. direction control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6. current levels under recommended operating conditions (t a = ?40 c to 85 c) . . . . . . . 11 table 7. components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 8. emi filter attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 9. dc voltage levels on host cpu side (t a = ?40 c to 85 c) . . . . . . . . . . . . . . . . . . . . . . . 14 table 10. dc voltage levels on sd card side (t a = ?40 c to 85 c) . . . . . . . . . . . . . . . . . . . . . . . . 14 table 11. leakage and short-circuit currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 12. ac characteristics (t a = ?40 c to 85 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 13. v ccb selection (b-side power supply voltage), en pin control . . . . . . . . . . . . . . . . . . . . . . 19 table 14. ldo static parameters (v en = v cca unless otherwise specified). . . . . . . . . . . . . . . . . . . . 20 table 15. ldo dynamic parameters (v en = v cca unless otherwise specified) . . . . . . . . . . . . . . . . . 20 table 16. package mechanical data for flip chip 25 (2 mm x 2 mm x 0.605 mm, 0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 17. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
list of figures st6g3244me 4/27 doc id 022157 rev 2 list of figures figure 1. pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. circuit diagram of st6g3244me (without ldo). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. symbol definitions of t plh , t phl , t r and t f for ac characteristics . . . . . . . . . . . . . . . . . . . . . 15 figure 6. test circuit from host to sd card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 7. test circuit from sd card to host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 8. example of measurement of t skew (sd card to host) from rising edge clk.h . . . . . . . . . 17 figure 9. example of measurement of t skew for read mode from rising edge clk.h . . . . . . . . . . . . 18 figure 10. low drop-out voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 11. package outline for flip chip 25 (2 mm x 2 mm x 0.605 mm, 0.4 mm pitch) . . . . . . . . . . . 23 figure 12. footprint recommendation for flip chip 25 (2 mm x 2 mm x 0.605 mm, 0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 13. pin 1 orientation in tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
st6g3244me description doc id 022157 rev 2 5/27 1 description the st6g3244me is a dual supply, low voltage 6-bit bi-directional cmos level translator for sd, mini sd and micro sd cards. designed for use as an interface between baseband and memory cards, it achieves high speed operation while maintaining cmos low-power dissipation. the a-port is designed to track v cca . the internal ldo is powered by v bat and provides a power supply of either 1.8 v or 2.9 v to the b-side i/os (programmed by the sel pin). the b-port is designed to track v ccb . the v ccb voltage can be also used externally. when v ccb = 0 v, there is no additional leakage seen on v cca . all outputs are push-pull type. this device is intended for two-way asynchronous communication between data buses. the direction of data transmission is determined by cmd.dir, dat0.dir and dat123.dir inputs. all inputs are equipped with protection circuits against electrostatic discharge, giving them 2 kv (on a-side) and 15 kv (on b-side, cd and wp) esd and transient excess voltage immunity.
functional description st6g3244me 6/27 doc id 022157 rev 2 2 functional description figure 1. pin connections dat2.h dat 3 .h cmd.h dat0.h dat1.h v cca clk.h clk-f gnd dat0.dir v ccb_out v bat en cmdb a b c d e 12 3 4 cmd.dir cd dat12 3 .di r gnd wp dat2b dat 3 b clkb dat0b dat1b 5 dat2.h dat 3 .h cmd.h dat0.h dat1.h v cca clk.h clk-f gnd dat0.di r v ccb_out v bat en cmdb a b c d e 54 3 2 cmd.di r cd dat12 3 .dir gnd wp dat2b dat 3 b clkb dat0b dat1b 1 top thro u gh view b u mp s ide view s el s el am04955v1 table 2. signal names (1) pin name bump type side description v cca b3 input a host side positive power supply (1.8 v) v ccb_out b4 output b internal supply voltage decoupling, v ccb ldo output v bat a4 input a battery power supply (3.0 - 5.0 v) gnd c4 ground - ground gnd c3 ground - ground en c2 input a enable, active-high sel b2 input a v ccb selection (b-side supply voltage, 1.8 v/2.9 v) cmd.dir a2 input a command direction control cmd.h d2 i/o a host side command clk.h c1 input a host side clock input clk-f e2 output a clock feedback to host dat0.dir a3 input a dat0 direction control dat0.h d1 i/o a host side data input/output dat123.dir e3 input a dat1, dat2, dat3 direction control dat1.h e1 i/o a host side data input/output
st6g3244me functional description doc id 022157 rev 2 7/27 dat2.h a1 i/o a host side data input/output dat3.h b1 i/o a host side data input/output wp e4 input to cpu a write protect cd d3 input to cpu a card detect cmdb d4 i/o b card side command clkb c5 output b card side clock output dat0b d5 i/o b card side data input/output dat1b e5 i/o b card side data input/output dat2b a5 i/o b card side data input/output dat3b b5 i/o b card side data input/output 1. collective names are used for groups of pins in the datasheet: *.dir = cmd.dir, dat0.dir, dat123.dir *.h = cmd.h, clk.h, dat0.h, dat1.h, dat2.h, dat3.h *b = cmdb, clkb, dat0b, dat1b, dat2b, dat3b v ia = all a-side input pins. table 2. signal names (continued) (1) pin name bump type side description table 3. direction control command signals direction of a-side signals (1) direction of b-side signals (1) en cmd.dir dat0.dir dat123.dir cmd.h clk.h clk-f dat0.h dat1.h dat2.h dat3.h cmdb clkb dat0b dat1.b dat2.b dat3.b h h x x in in out x x out out x x hl x x outinoutx x inoutx x h x h x x in out in x x out out x h x l x x in out out x x out in x h x x h x in out x in x out x out h x x l x in out x out x out x in lx x x xxzx x (2) z (2) (2) 1. when the direction of the a-side signal is input, the host cpu writes to the sd card (i.e. the direction of the b-side signal is output). when the direction of the a-side signal is output, the host cpu reads the sd card (i.e. the direction of the b-side signal is input). 2. level of the b-side signals when en = l is defined by the internal resistors as listed in table 7 . note: during application design it has to be considered that the level shifter device needs some time to change the direction after a change of the .dir signal level. valid data on the input of the corresponding channel can then start after a turn-around time, see the t ta specification in ta bl e 1 2 .
functional description st6g3244me 8/27 doc id 022157 rev 2 figure 2. block diagram en v cc a v cca r en 500 k v ccb a v bat ref tsd uvlo 15 kv v ccb out cmd.dir cmd.h cmdb v ccb 15 k r9 15 kv clk.h clkb 15 kv clk-f v cca dat0.dir dat0.h dat0b v ccb 70 k r10 15 kv dat123.dir dat1.h dat1b v ccb 70 k r11 15 kv dat2.h dat2b v ccb 70 k r12 15 kv dat3.h dat3b 470 k r7 15 kv v cca 100 k r14 wp v cca 100 k r13 cd 15 kv 15 kv gnd ldo emi filters level translator sel r sel 500 k r pd 130 v ccb 2 kv 2 kv 2 kv 2 kv 2 kv 2 kv 2 kv 2 kv 2 kv 2 kv 2 kv 2 kv 2 kv 2 kv r, c am04956v2
st6g3244me functional description doc id 022157 rev 2 9/27 figure 3. typical application diagram 1. can be used externally, however, note that it follows v ccb value that is switched between 2.9 and 1.8 v by the sel pin. ho s t cpu s d c a rd low drop-o u t volt a ge reg u l a tor ldo e s d 15 kv a nd emi clk.h clk-f cmd.dir cmd.h dat0.dir dat0.h dat12 3 .dir dat1.h dat2.h dat 3 .h dat1b dat2b dat 3 b dat0b cmdb clkb dat1b dat2b dat 3 b dat0b cmdb clkb v bat ( 3 .0 ? 5.0 v) v cca wp wp en s el v ccb e s d 2kv v (2.9/1. 8 v) (1) ccb_out gnd s t6g 3 244me cd cd c bat c vcca s el gnd c vccb e s d 15 kv am04957v4 e s d 15 kv
maximum ratings st6g3244me 10/27 doc id 022157 rev 2 3 maximum ratings stressing the device above the rating listed in table 4: absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in table 5: recommended operating conditions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 4. absolute maximum ratings symbol parameter value unit t jmax maximum junction temperature 150 c r th(j-a) (1) thermal resistance from junction to ambient (board: epoxy fr4, e (cu) = 40 m, 4 layers) 64 c/w p dmax maximum power dissipation: p dmax = (t jmax - t amax )/r th(j-a) 1w t stg storage temperature range ?55 to 150 c v cca power supply ?0.3 to 4.6 v v bat battery power supply ?0.3 to 5.5 v v io cmdb, clkb, dat0b, dat1b, dat2b, dat3b ?0.3 to v ccb + 0.3 v v cca , sel, en ?0.3 to 4.6 cmd.dir, cmd.h, clk.h, clk-f, dat0.dir, dat0.h, dat123.dir, dat1.h, dat2.h, dat3.h, wp, cd ?0.3 to v cca + 0.3 esd a-side (host cpu), all pins: v cca , en, sel, dat123.dir, cmd.dir, cmd.h, clk.h, clk-f, dat0.dir, dat0.h, dat1.h, dat2.h, dat3.h, v bat hbm jedec 22-a114 2kv mm jedec 22-a115 200 v b-side (sd card), external pins: cmdb, clkb, dat0b, dat1b, dat2b, dat3b, wp, cd, v ccb_out air discharge iec61000-4-2 15 kv contact discharge iec61000-4-2 8 kv 1. the thermal resistance depends on the printed circuit board layout. to dissipate the heat efficiently away from the flip-chip bumps, it is recommended to make the copper planes as large as possible and consider using thermal vias.
st6g3244me dc and ac parameters doc id 022157 rev 2 11/27 4 dc and ac parameters table 5. recommended operating conditions symbol parameter conditions min. typ. max. unit v cca power supply 1.62 1.8 1.98 v v bat battery power supply 3.0 5.0 v c bat external battery capacitance ceramic capacitor 1.0 2.2 2.8 f c vcca v cca decoupling capacitor ceramic capacitor 0.1 f c vccb internal supply voltage (v ccb ) decoupling capacitor ceramic capacitor 1.0 2.2 2.8 f t a ambient operating temperature ?40 25 85 c t j junction operating temperature ?40 25 125 c p d maximum power dissipation p d = (t j - t a )/r th(j-a) 625 mw v io_b i/o voltage on external pins (without wp and cd) - b-side cmdb, clkb, dat0b, dat1b, dat2b, dat3b 0v ccb v v io_a i/o voltage on internal pins (includes wp and cd) - a-side en, sel, wp, cd, dat123.dir, cmd.dir, cmd.h, clk.h, clk-f, dat0.dir, dat0.h, dat1.h, dat2.h, dat3.h 0v cca v table 6. current levels under recommended operating conditions (t a = ?40 c to 85 c) symbol parameter test conditions (1) min. typ. max. unit i q_off quiescent current consumption i cca_off v en = 0.4 v, v bat = 3.4 v, v cca = 1.98 v *.dir, *b = 0 v, wp = cd = v cca all other pins floating 1a quiescent current consumption i bat_off 1a i q_on quiescent current consumption (ground pin current) i bat + i cca *.dir = 0 v, v bat = 3.4 v v en = v cca = v clk.h = 1.98 v all other pins floating i out = 100 a 150 (2) a i out = 50 ma 250 (2) i cca_on quiescent current on v cca v en = v cca = 1.92 v, v bat = 3.4 v, *.dir = v cca , v ia = *.h = v cca 310a 1. collective names for groups of pins: *.dir = cmd.dir, dat0.dir, dat123.dir *.h = cmd.h, clk.h, dat0.h, dat1.h, dat2.h, dat3.h *b = cmdb, clkb, dat0b, dat1b, dat2b, dat3b v ia = all a-side input pins. 2. guaranteed by design.
passive integration and low-pass emi filter st6g3244me 12/27 doc id 022157 rev 2 5 passive integration and low-pass emi filter figure 4. circuit diagram of st6g3244me (without ldo) r6 r7 r5 r4 r 3 r2 r1 clkb cmdb dat0b dat1b dat2b dat 3 b 15 kv r9 r10 r11 r12 v ccb r en clk.h cmd.h dat0.h dat1.h dat2.h dat 3 .h en r1 3 v cca wp cd 15 kv 15 kv s d c a rd s ide level tr a n s l a tor ho s t s ide 15 kv gnd e s d 2 kv r14 s el r s el gnd am0495 8 v2
st6g3244me passive integration and low-pass emi filter doc id 022157 rev 2 13/27 table 7. components symbol parameter test conditions (1) min. typ. max. unit c in-a input capacitance for a-side v bat = 3.4 v, *.dir = v en = v cca f = 1 mhz, v dc = 0 v 30 mv, v ac = 30 mv 510pf c in-b input capacitance for b-side v bat = 3.4 v, *.dir = 0 v, v en = v cca f = 1 mhz, v dc = 0 v 30 mv, v ac = 30 mv 24 28 pf r1, r2, r3, r4, r5, r6 (2) emif resistors t j = 25 c 32 40 48 r10, r11, r12 dat0b, dat1b, dat2b pull-up resistors t j = 25 c 49 70 91 k r9 cmdb pull-up resistor t j = 25 c 10.5 15 19.5 k r7 dat3b pull-down resistor t j = 25 c 329 470 611 k r13 cd pull-up resistor t j = 25 c 70 100 130 k r14 wp pull-up resistor t j = 25 c 70 100 130 k r pd ldo resistor t j = 25 c 90 130 170 r en en pull-down resistor t j = 25 c 500 k r sel sel pull-down resistor t j = 25 c 500 k 1. see note 1 on page 7 for definition of collective names of pins, for example *.dir. 2. these values are guaranteed by design and statistical process control. table 8. emi filter attenuation symbol parameter test conditions min. typ. max. unit il 0-200m filter attenuation (1) frequency range: 0 hz to 200 mhz 6 - - db il 401-800m frequency range: 401 mhz to 800 mhz 10 - - il 801-2500m frequency range: 801 mhz to 2.5 ghz 20 - - il 2600-6000m frequency range: 2.6 ghz to 6 ghz 30 - - 1. guaranteed by design.
data transmission st6g3244me 14/27 doc id 022157 rev 2 6 data transmission all values in the tables below are guaranteed across the operating temperature and voltage range unless otherwise specified. table 9. dc voltage levels on host cpu side (t a = ?40 c to 85 c) symbol parameter test condition min. typ. max. unit v iha high level input voltage 0.65 v cca v cca v v ila low level input voltage 0 0.35 v cca v v oha high level output voltage i oh = ?6 ma, v cca = 1.62 v v cca ? 0.45 v cca v v ola low level output voltage i ol = 7 ma, v cca = 1.62 v 00.45v table 10. dc voltage levels on sd card side (t a = ?40 c to 85 c) symbol parameter test condition min. typ. max. unit v ihb high level input voltage 0.7 v ccb v ccb v v ilb low level input voltage 0 0.3 v ccb v v ohb high level output voltage i oh = ?4 ma 0.8 v ccb v ccb v v olb low level output voltage i ol = 4 ma 0 0.2 v ccb v table 11. leakage and short-circuit currents symbol parameter test condition (1) 1. collective names for groups of pins: *.dir = cmd.dir, dat0.dir, dat123.dir *.h = cmd.h, clk.h, dat0.h, dat1.h, dat2.h, dat3.h *b = cmdb, clkb, dat0b, dat1b, dat2b, dat3b v ia = all a-side input pins. min. typ. max. unit i lh leakage current on host side pins v sel = 0 v, v en = *.dir = v cca = 1.98 v v ia = v cca or 0 v, v bat = 3.4 v 5a i lsd leakage current on sd card side pins v sel = 0 v, v bat = 3.4 v, v clk.h = v cca v cmd = v dat0 = v dat1 = v dat2 = v ccb v dat3 = *.dir = 0 v 5a i sch short-circuit current on host side pins sd card input = h, host = 0 v sd card input = 0 v, host = v cca = 1.8 v *.dir = 0 v, v bat = 3.4 v, t j = 25 c 25 ma i scsd short-circuit current on sd card side pins host input = h, sd card = 0 v host input = l, sd card = v ccb = 2.9 v, t j = 25 c, *.dir = v cca = 1.8 v, v bat = 3.4 v 25 70 ma host input = h, sd card = 0 v host input = l, sd card = v ccb = 1.8 v, t j = 25 c, *.dir = v cca = 1.8 v, v bat = 3.4 v 25 70
st6g3244me data transmission doc id 022157 rev 2 15/27 figure 5. symbol definitions of t plh , t phl , t r and t f for ac characteristics input output 50 % 50 % 50 % 50 % 20 % 20 % 80 % 80 % v cca or v ccb 0 v v cca or v ccb 0 v t r t f t plh t phl am04959v1 table 12. ac characteristics (t a = ?40 c to 85 c) symbol parameter test condition min. typ. max. unit t phl propagation delay hl from host to sd see section 6.1 v ccb = 1.8 v 3.2 7 ns v ccb = 2.9 v 3.2 5 t plh propagation delay lh from host to sd see section 6.1 v ccb = 1.8 v 3.2 7 ns v ccb = 2.9 v 3.2 5 t phl propagation delay hl from sd to host see section 6.2 v ccb = 1.8 v 3.0 7 ns v ccb = 2.9 v 2.8 5 t plh propagation delay lh from sd to host see section 6.2 v ccb = 1.8 v 3.0 7 ns v ccb = 2.9 v 2.8 5 t r rise time from host to sd see section 6.1 v ccb = 1.8 v 2.0 4 ns v ccb = 2.9 v 2.0 4 rise time from sd to host see section 6.2 v ccb = 1.8 v 2.0 4 v ccb = 2.9 v 2.0 4 t f fall time from host to sd see section 6.1 v ccb = 1.8 v 2.0 4 ns v ccb = 2.9 v 2.0 4 fall time from sd to host see section 6.2 v ccb = 1.8 v 2.0 4 v ccb = 2.9 v 2.0 4 t ta turn-around time (direction switch response, for all channels) (1) v ccb = 1.8 v or 2.9 v, c l = 15 pf 7.5 12 ns t skew delay differences from host to sd see section 6.1 see section 6.3 ?0.5 0 0.5 ns t ch2ch-skew channel-to-channel skew ?0.5 0 0.5 ns t skew.f clk-f to cmd, dat delay (valid for pcb trace lengths from 20 mm to 100 mm) see section 6.2 see section 6.4 0.3 1.2 ns t p_clkf propagation delay from clk feedback see section 6.2 v ccb = 1.8 v 5.7 13.5 ns v ccb = 2.9 v 5.5 9.5
data transmission st6g3244me 16/27 doc id 022157 rev 2 6.1 test circuit from host to sd card the test circuit from the host to the sd card is shown in figure 6 . timings are measured for the whole line cell (translator + emi + esd) on an external load c sd = 15 pf (board capacitance 5 pf + sd card capacitance 10 pf). figure 6. test circuit from host to sd card 6.2 test circuit from sd card to host the test circuit from the sd card to the host is shown in figure 7 . timings are measured for the whole line cell (translator + emi + esd) on an external load c host = 10 pf (board capacitance + host capacitance). figure 7. test circuit from sd card to host t r_clkf rise time for clk feedback see section 6.2 v ccb = 1.8 v 1.0 3 ns v ccb = 2.9 v 1.0 3 t f_clkf fall time for clk feedback see section 6.2 v ccb = 1.8 v 1.0 3 ns v ccb = 2.9 v 1.0 3 f max clock rate 60 mhz data rate 120 mbps 1. the time after the .dir signal transition that the device needs to switch direction, after that it is ready to accept valid d ata on the switched input. table 12. ac characteristics (t a = ?40 c to 85 c) (continued) symbol parameter test condition min. typ. max. unit host sd card c sd = 15 pf am04960v2 host sd card c host = 10 pf am04961v2
st6g3244me data transmission doc id 022157 rev 2 17/27 6.3 measurement of t skew (sd card to host) from rising edge clk.h figure 8. example of measurement of t skew (sd card to host) from rising edge clk.h 15 pf dela y 15 pf sd c c c c c c c ca ca ca a a a a a r r r r r r c c c c c c c ca ca a ca a a a a r r r r r r r card st6g3244me cpu clk.h clk-f datx.dir = 1 b x t a d h . x t a d clkb 50 % v cc a 0 v datx.h 50 % v ccb 0 v datxb t p ( datx.h -> datxb ) 50 % v cc a 0 v clk.h 50 % v ccb 0 v clkb t p ( clk.h -> clkb ) t skew = t p ( clk.h -> clkb ) C t p ( datx.h -> datxb ) am04962v2
data transmission st6g3244me 18/27 doc id 022157 rev 2 6.4 measurement of t skew.f (read mode) from rising edge clk.h figure 9. example of measurement of t skew for read mode from rising edge clk.h datx.h = dat0.h, dat1.h, dat2.h, dat3.h, cmd.h datxb = dat0b, dat1b, dat2b, dat3b, cmdb 15 pf dela y 10 pf sd card st6g3244me cpu clk.h clk-f datx.dir = 0 b x t a d h . x t a d clkb 50 % v cc a 0 v datx.h 50 % v ccb 0 v datxb 50 % v cc a 0 v clk.h 50 % v ccb 0 v clkb t p ( clk.h -> clkb ) 10 pf t skew.f = [ t p(clk.h -> clkb) + t p(datxb -> datx.h) ] C t p(clk.h -> clk-f) 50 % v cc a 0 v clk-f t p ( clk.h -> clk-f ) t p ( datxb -> datx.h ) am0496 3 v2
st6g3244me low drop-out voltage regulator doc id 022157 rev 2 19/27 7 low drop-out voltage regulator figure 10. low drop-out voltage regulator baseband asic v bat v cca v ccb_out r, c v bat level translator 15 kv st6g3244me ? ldo + - r en 500 k c bat c vcca v cca v ccb gnd c vccb v en en r pd 130 r sel 500 k sel v sel 2 kv 2 kv 2 kv v ccb uvlo logic tsd a am04964v2 table 13. v ccb selection (b-side power supply voltage), en pin control en sel v ccb (1) (v) 0x 0 (2) 10 2.9 11 1.8 1. v ccb is an internal b-side i/o power supply, tied to the v ccb_out pin for external decoupling capacitor. v ccb supply voltage can also be used externally. 2. pulled down to gnd by r pd . when v ccb = 0 v, no additional leakage is seen on v cca .
low drop-out voltage regulator st6g3244me 20/27 doc id 022157 rev 2 note: level translator deactivated, *.dir = 0, clk.h = v cca , all other pins floating. table 14. ldo static parameters (v en = v cca unless otherwise specified) symbol parameter test condition min. typ. max. unit v ccb_o ut regulated output voltage (v ccb ) v bat = 3 to 5 v, sel = 0 i out = 0.1 to 50 ma, t j = ?40 to 125 c 2.75 2.90 3.05 v v bat = 3 to 5 v, sel = 1 i out = 0.1 to 50 ma, t j = ?40 to 125 c 1.71 1.8 1.89 v do drop-out voltage v ccb_out (nom) ? 100 mv t j = ?40 to 85 c sel = 0 i out = 50 ma 25 40 mv i out v ccb_out output current 50 ma tsd thermal shutdown temperature v bat = 3.4 v shutdown (temp. ) 150 c reset (temp. ) 130 hysteresis 20 uvlo undervoltage lockout t j = ?40 to 125 c shutdown (v bat ) 2.3 2.5 2.7 v reset (v bat ) 2.35 2.55 2.75 v hysteresis 50 mv table 15. ldo dynamic parameters (v en = v cca unless otherwise specified) symbol parameter test condition min. typ. max. unit psrr power supply rejection ratio v bat = 3.4 v i out = 50 ma t j = 25 c c vccb = 2.2 f, esr = 5 m f = 1 khz 40 db f = 10 khz 30 t start settling time v ccb_out 95% nom., v bat = 5 v, i out = 50 ma, t j = ?40 c to 125 c, c vccb = 1 f, enable l h, sel = 0 30 100 s v ccb_out 95% nom., v bat = 5 v, i out = 50 ma, t j = ?40 c to 125 c, c vccb = 1 f, enable l h, sel = 1 30 100 t stop discharge time v ccb_out 10% nom., v bat = 3.4 v, i out = 1 ma, t j = 25 c, c vccb = 1 f, enable h l, sel = 0 0.6 1 ms v ccb_out 10% nom., v bat = 3.4 v, i out = 1 ma, t j = 25 c, c vccb = 1 f, enable h l, sel = 1 0.6 1
st6g3244me sd card specification compliance doc id 022157 rev 2 21/27 8 sd card specification compliance the st6g3244me is designed to be compliant with sd card specifications. the reference standards used include: sd card specification v3.00 (sdr12, sdr25, ddr50) sd card specification v2.00 the clock and data channels are designed to meet a 60 mhz clock rate and 120 mbps data rate respectively to support both sdr and ddr modes.
package mechanical data st6g3244me 22/27 doc id 022157 rev 2 9 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
st6g3244me package mechanical data doc id 022157 rev 2 23/27 figure 11. package outline for flip chip 25 (2 mm x 2 mm x 0.605 mm, 0.4 mm pitch) note: the terminal a1 is on the top side of the package identified by a circular dot - typically 0.5 mm in diameter. 7499669_e(a) table 16. package mechanical data for flip chip 25 (2 mm x 2 mm x 0.605 mm, 0.4 mm pitch) symbol millimeters min. typ. max. a 0.560 0.605 0.650 a1 0.180 0.205 0.230 a2 0.380 0.400 0.420 b 0.230 0.255 0.280 d 1.985 2.00 2.015 d1 1.59 1.60 1.61 e 1.985 2.00 2.015 e1 1.59 1.60 1.61 e 0.36 0.40 0.44 f 0.190 0.200 0.210 ccc 0.05
package mechanical data st6g3244me 24/27 doc id 022157 rev 2 figure 12. footprint recommendation for flip chip 25 (2 mm x 2 mm x 0.605 mm, 0.4 mm pitch) 7499669_e(a)
st6g3244me tape and reel information doc id 022157 rev 2 25/27 10 tape and reel information figure 13. pin 1 orientation in tape am07567 top view of package - balls underneath. pin 1 marked from target specification. direction of flow in accordance to eia 481-c-2003 25 pin bga 5 x 5 square device in quadrant 1.
revision history st6g3244me 26/27 doc id 022157 rev 2 11 revision history + table 17. document revision history date revision changes 25-aug-2011 1 initial release. 08-nov-2011 2 removed label ?custom data?, updated features , applications , ta b l e 1 updated and moved from section 11 package marking on page 26 to page 1, updated section 1: description , section 2: functional description , table 2 , ta b l e 3 to ta ble 7 , ta b l e 1 0 to ta b l e 1 2 , ta b l e 1 4 , figure 8 , figure 9 , figure 13 , removed section 11 package marking , minor text corrections throughout document.
st6g3244me doc id 022157 rev 2 27/27 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at an y time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2011 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of ST6G3244MEBJR

	To Download ST6G3244MEBJR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .